8/15/2023 0 Comments Tick tock closegavbon86: RT ASRock Unveils Z790 and B650E Taichi Lite Motherboards: Taichi Goes Lite. ![]() While I have no proof of this, based on Keller's track record it stands to reason that he would clearly want to work on Ocean Cove, not polish Golden Cove whether his presumed request was granted by Intel's upper management is unknown though. When Keller was hired by Intel the design of Ocean Cove was just starting but the design of Golden Cove was largely complete. Jim Keller is not in the habit of optimizing designs of others his expertise is in designing / leading the design of *new* designs. The ad was soon pulled (it appears that the Ocean Cove name was leaked prematurely by mistake) but since it was published just a few days after (or before, cannot quite recall) Intel announced Keller was joining the company the link between the two was unstated but obvious. Back when Keller's hiring was announced Intel also published a LinkedIn ad asking for microprocessor engineers for the design of "Ocean Cove", which was first mentioned by name then. Santoval - Wednesday, Malink Most likely the design of Golden Cove (the "big" cores of Alder Lake) was largely "locked" when Jim Keller joined Intel - at most it required optimizations and "trimming".With any luck, if Intel can get a headwind with 7nm, when 2024 rolls around it might all come thick and fast. It’s been known that Intel’s microarchitecture teams haven’t been idle waiting for 10nm to come through the pipe, with a number of designs ready and waiting to go for when the process node technology matures. Tiles by this definition are more costly to implement than chiplets, and have additional thermal considerations by having high-powered silicon close together, so it will be interesting to see how Intel balances these new packaging technologies with the more cost-sensitive elements of its portfolio, such as client processors. This is because Intel’s tiles amount to long wires across 3D packaging technologies like EMIB and Foveros, compared to package-based multi-die interconnect that require buffers as well as control fabric. It is also worth noting that Intel/Gelsinger isn’t calling its disaggregated silicon as ‘chiplets’, and prefers to use the term ‘tiles’. Intel has also stated that it is looking to consider the core of its leading edge compute on external foundry processes, although one might argue that this doesn’t explicitly say ‘CPU’. Intel stated that its 7nm process is now comfortably on track to deliver Meteor Lake, a client CPU using tiles/chiplets, in 2023, however we are likely looking to a 7nm variant or even external processes for a 2024/2025 product. ![]() This is for sure a laudable goal, however Intel will also have to adapt to a changing landscape of chiplet processor designs (coming in 2023), enhancing on-die accelerators (GNA already present), and also what it means to have leadership performance – in the modern era, leadership performance doesn’t mean much if you’re also pushing lots of Watts. The company is thus looking to 2024/2025 for ‘unquestioned CPU leadership performance’, which traditionally means the fastest processor for single thread and multi-thread workloads. On top of this commentary, Pat Gelsinger also stated that Intel’s CPU roadmaps are already baked in through 2021, 2022, and 2023. Pat stated as part of the call that Intel will look towards a confirmed yearly process node improvement, and as a result, there might be a lot of Ticks in the future, with a push to more Tocks as well. ![]() Part of this is re-establishing discipline in Intel’s ranks to continually provide both microarchitecture updates and process node updates on a regular expected cadence. ![]() Today CEO Pat Gelsinger stated that at Intel’s core it has to re-establish the Tick-Tock model that enabled repeated leadership in the CPU ecosystem, buoyed by a healthy CPU roadmap. That policy was scuppered when delays to Intel’s 10nm forced Intel into more of a Tick-Tock-Optimization-Optimization-Optimization model. Each generation would alternate between the two, allowing Intel to take advantage of a familiar design on a new process node, or using a mature node to enable a new performance-focused design. This means that for every product generation, the leading edge compute hardware was either a Tick (process node enhancement), or a Tock (microarchitecture enhancement). In the past, through the 1990s, 2000s, and into the 2010s, Intel’s manufacturing philosophy was known as ‘Tick-Tock’. One of Gelsinger’s mantras seems to be that unquestioned leadership products bring unquestioned leadership margins for those products, and for Intel to execute, it needs to return to its days of old. As part of today’s announcements, during Intel’s Q&A session after the prepared remarks, CEO Pat Gelsinger explained how Intel is going to revive its fortunes when it comes to its leading edge compute products.
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